Design and verification IP reuse is a significant concept in solving the
fnctional verification bottleneck. Our product development effort is
focused on building verification components using SystemVerilog
and e hardware verification language. We provide utility packages
and verification components for popular interfaces.
For more information about these products, follow one of the links below:
The UART SystemVerilog verification component is a ready-made,
highly configurable verification environment suitable for any DUT
that contains an UART interface. This component supports a number
of different UART models.
The SystemVerilog UART verification component can:
Be configured to model any of 16550, 16650, 16750, or 16950 UART models.
Generate and drive frame traffic as an UART transmitter.
Respond to frame traffic as an UART receiver.
Update the internal status registers based on conditions.
Monitor, check, and cover frame traffic.
The UART eVC is a ready-made, highly configurable e verification environment suitable for any DUT that contains an UART interface. This eVC supports a number of different UART models.
Ethernet eVC:
The si_eth8023 eVC is a ready-made, highly configurable e verification environment suitable for any DUT that contaSins an Ethernet interface.
This eVC supports all instantiable interfaces of Ethernet over the 10M/100M/ 1G/10G operating speeds.
The si_eth8023 eVC:
Supports all instantiable interfaces defined by the IEEE 802.3 specification.
Generates and drives bus traffic as an Ethernet transmit channel over all supported ethernet interface layers.
Responds to bus traffic and performs validity check for all normal and encoded data frames defined by the specification.
Can inject errors to emulate all erroneous operational conditions observed during device operation.
Monitors, checks, and collects coverage on bus traffic.
Models Half/Full duplex operation.
Physical medium modeled as fabric allowing deterministic and random behavior modeling.
e Utility Package
This utility package is designed to enhance the core functionality of the e language and to also provide useful data structures and modules that help streamline the development of a verification environment. The main features of this package are listed below.
