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12.20.2006 SiMantis' si_util e Utility Package (eUP) is described in an article appearing in the December issue of Cadence Incisive Newsletter.
10.01.2006 SiMantis Inc. Announces the availability of si_uart_sv, an SystemVerilog based verification component for the UART interface.

09.01.2006 SiMantis Inc. publishes paper at CDN Live 2006 on native handling of simulation time in the e verification language.


A leading provider of electronic design expertise, services, and resources, SiMantis works directly with fortune 500 and startups to enhance and augment the design and development effort from specification to tape out.

At SiMantis, our focus is on reducing development time while delivering quality and value. The core of our business is concentrated on:





“Step-by-Step Functional Verification with SystemVerilog and OVM”

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