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12.20.2006 SiMantis' si_util e Utility Package (eUP) is described in an article appearing in the December issue of Cadence Incisive Newsletter.
10.01.2006 SiMantis Inc. Announces the availability of si_uart_sv, an SystemVerilog based verification component for the UART interface.

09.01.2006 SiMantis Inc. publishes paper at CDN Live 2006 on native handling of simulation time in the e verification language.


The Challenge: Competition is tough in the electronics industry and the key to success seems to be in building ever more complex designs even faster than that last design you recently completed!

The challenge is to simultaneously address 3 competing priorities:

  • To Increase Productivity
  • To Improve Quality
  • To Add Complexity
This challenge can be overcome only through a conscious dedication to improving state of the art in electronics design.

At SiMantis, we believe that the design productivity challenge is best addressed through a multi-faceted strategy consisting of:

  • Using the latest EDA tools that facilitate new abstractions and methodologies.
  • Developing new methodologies that increase productivity and design quality.
  • Taking design reuse to the limit.
  • Arming design teams with new tools and techniques through effective training.

We turn our business strategy into tangible results for our customers by providing the following services and resources:

  • Methodology Consulting
  • Turnkey Design Services
  • Technical Staff Resources
  • Verification IP
  • Tools and Methodology Training

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