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12.20.2006 SiMantis' si_util e Utility Package (eUP) is described in an article appearing in the December issue of Cadence Incisive Newsletter.
10.01.2006 SiMantis Inc. Announces the availability of si_uart_sv, an SystemVerilog based verification component for the UART interface.

09.01.2006 SiMantis Inc. publishes paper at CDN Live 2006 on native handling of simulation time in the e verification language.


Ideal Candidates:

We are currently looking to fill contract and full time positions. We are looking for engineers that posess excellent analytical and communication skills and have working experience in one or more of the following fields:

  • Verification using Specman Elite or Verilog PLI
  • In-depth knowledge of e Reuse Methodology and experience in eVC development
  • Full spectrum of DFT project responsibilities
  • In-depth knowledge of Ethernet
  • In-depth knowledge of PCI-Express
  • In-depth knowledge of SATA
  • Functional design experience in networking or consumer electronics domains
  • High Speed design expertise
  • Memory cache design experience

To be considered for a job openning, please email your resume to jobs@simantis.com with a brief description of your desired position.

Job Openings:

Job descriptions to be posted shortly.

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