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12.20.2006 SiMantis' si_util e Utility Package (eUP) is described in an article appearing in the December issue of Cadence Incisive Newsletter.
10.01.2006 SiMantis Inc. Announces the availability of si_uart_sv, an SystemVerilog based verification component for the UART interface.

09.01.2006 SiMantis Inc. publishes paper at CDN Live 2006 on native handling of simulation time in the e verification language.


“Step-by-Step Functional Verification with SystemVerilog and OVM”
Step-by-Step Functional Verification with SystemVerilog and OVM
 Hard Cover: 520 pages
Publisher: Hansen Brown Publishing
Date: May 2008
Language: English
ISBN-10: 0-9816562-1-8
ISBN-13: 978-0-9816562-1-2
Ships in the last week of May 2008
List Price: $139.00
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